Rapid Prototyping of Digital Systems,

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RAPID PROTOTYPING
OF DIGITAL SYSTEMS
Second Edition
A Tutorial Approach
RAPID PROTOTYPING
OF DIGITAL SYSTEMS
Second Edition
A Tutorial Approach
James O. Hamblen
Georgia Institute of Technology
Michael D. Furman
Georgia Institute of Technology
KLUWER ACADEMIC PUBLISHERS
NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW
eBook ISBN:
0-306-47635-5
Print ISBN:
0-7923-7439-8
©2002 Kluwer Academic Publishers
New York, Boston, Dordrecht, London, Moscow
Print ©2001 Kluwer Academic Publishers
Dordrecht
All rights reserved
No part of this eBook may be reproduced or transmitted in any form or by any means, electronic,
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Created in the United States of America
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Table of Contents
1 Tutorial I: The 15 Minute Design
2
1.1
1.2
1.3
1.4
Design Entry using the Graphic Editor
Compiling the Design
Simulation of the Design
6
9
10
12
14
Downloading Your Design to the UP 1 or UP 1X Board
1.5
1.6
The 10 Minute VHDL Entry Tutorial
Compiling the VHDL Design
17
17
21
22
23
1.7
1.8
1.9
1.10
1.11
The 10 Minute Verilog Entry Tutorial
Compiling the Verilog Design
Timing Analysis
The Floorplan Editor
Symbols and Hierarchy
24
24
25
25
1.12
1.13
1.14
Functional Simulation
For additional information
Laboratory Exercises
2 The Altera UP 1 and UP 1X CPLD Boards
2.1
2.2
2.3
2.4
2.5
30
Programming Jumpers
MAX 7000 Device and UP 1 I/O Features
MAX and FLEX Seven-segment LED Displays
FLEX 10K Device and UP 1 I/O Features
Obtaining a UP 1 or UP 1X Board and Power Supply
31
31
31
34
36
3 ProgrammableLogic Technology
3.1
3.2
3.3
3.4
38
CPLDs and FPGAs
Altera MAX 7000S Architecture – A Product Term CPLD Device
Altera FLEX 10K Architecture – A Look-Up Table CPLD Device
Xilinx 4000 Architecture – A Look-Up Table FPGA Device
41
42
43
47
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